Can it run DOOM? This is an entry for the Hackaday Retrocomputing Challenge by DigiKey, brought up on the Intel Cyclone IV (Terasic DE0-Nano) FPGA, building on the previous CPU work

I put my dual-issue RV32IM superscalar CPU, with custom UART, I2C, and FIFO IPs, on an FPGA and built a retro system around it. A launcher lets you choose between DOOM, a Wolfenstein-style raycaster, and custom games such as Snake, 2048, Tetris, Minesweeper, and Flappy Bird. It also runs classic 8-bit software in a CP/M 2.2 environment and CHIP-8 games through a software interpreter

The CPU runs from SDRAM, with programs and game data loaded over UART through a CP2102 USB-to-TTL adapter. Keyboard input comes back over the same link into a hardware key register with press and release events. Each tick, the core reads the input, updates the running program, and writes an 8-bit framebuffer to SDRAM. On a frame commit, the core clock briefly pauses to burst the frame into a TX FIFO, streaming it over UART at 45 FPS to a host RGB viewer. A monochrome version is also displayed at ~33 FPS on an SSD1306 OLED over I2C

Before putting it on hardware, I built the same system in Verilator, running DOOM at 1.38 IPC while keeping the same MMIO interface and replacing SDRAM and peripherals with testbench stand-ins. A fast harness with snapshot/restore made iteration much easier, and a web bridge let me play it directly in the browser

Getting everything onto the board meant cutting predictor tables, making wide multiply/divide iterative while keeping the fast path on DSPs (holding ~1.35 IPC after the cuts), retuning the serial framing, and repacking the game assets to fit in SDRAM. CoreMark CRC checks caught functional issues before I started debugging the game itself

Alongside this, I’ve also been extending the same CPU toward a simple Out-of-Order design to explore the Tomasulo algorithm through an intuitive walkthrough

PS. Full write-ups (design decisions, debugging): https://mummanajagadeesh.github.io/categories/riscv/

Hi everyone,

Just wanted to share a hobby project I’ve been working on: https://github.com/dxur/silane

It’s an organization of independent personal projects I put together into a public repo. The main piece is a custom hardware construction language, along with a RISC-V core and a VP8 video decoder written in it.

it is failing again and again download is not completing after a certain time can any one fix this issue.

INFO - There was an error downloading files and user did not want to retry.

ERROR - There is an error while downloading file: https://amd-ax-dl.entitlenow.com/dl/ul/2026/06/17/R212901111/shareddata_0251_2026.1_0616_1700.xz?hash=spJ_EOnlU7iog1Wx19xwhQ&expires=1793184176&filename=shareddata_0251_2026.1_0616_1700.xz&sessionid=ecfb7097-9dcc-46e1-82b0-6711b37f8ac1

I want to end up in design, that was always my end goal, however I’m currently unemployed and have been since graduating.

I now have an offer for a verification role, and I’m worried I end up stuck here, but obviously it’s always better than being unemployed.

Should I take this and work towards transferring to design somehow later down the line or hold out till I land a design role?

How doable is the transfer, 2-4 years down the line?

So I have found a Xilinx Spartan 3e starter kit board on sale for 25 euros, I currently have a tang nano 9k. Is it worth it? Is supported by some toolchain or is a museum piece?

I’m a senior working on my senior design project. My team is building a 2 channel 12-bit oscilloscope. The plan is a Zynq board where the FPGA does the capture and triggering, and the ARM side runs Linux for the measurements and display. We’re making our own front end and ADC board, and we’d like to stick with Xilinx since we already know Vivado.

We want 20 MHz bandwidth, so we picked a TI ADS62P24 running at 100 MS/s (about 5 samples per cycle at 20 MHz). The part I’m worried about is getting that data into the SoC board. In LVDS mode it’s 12 data pairs plus a clock pair at 200 Mb/s each, or 25 CMOS lines at 100 MHz if we go that route. We also need around 30 regular GPIO for knobs, buttons and relays, plus some kind of display output (HDMI would be nice). Budget for the board is about $350.

Right now we’re leaning toward the MYIR Z-turn V2 (Zynq-7020). Bank 35 has 24 pairs on its 1.27mm connectors and MYIR posts the trace lengths, but I can’t find anyone who’s actually pushed LVDS through it at this speed. We already ruled out the AUP-ZU3 since its Pmod+ header is only rated around 50 MHz, and the Eclypse Z7 is out of our budget.

Has anyone used the Z-turn V2 for something like this? Or is there another Zynq board around that price with FMC, SYZYGY, or a decent high speed connector that we’re missing? Any tips on LVDS capture on Zynq-7000 would be appreciated too.

I have meet my supervisor and he said that i need to remove my memories module for now. He also said that I need to learn more about the load signal in my register module. How to use the load in my testbench? I know load was used to keep my register on and off. The thing is after I removed my memories module, it still the same. It still double accumulated.

My modules:

• Adder module:

module Adder #(

parameter WIDTH = 16, // total bits including integer and fraction

parameter FRAC = 10 // fractional bits (Q6.10 -> FRAC=10)

)(

input signed [WIDTH-1:0] a,

input signed [WIDTH-1:0] b,

output signed [WIDTH-1:0] sum

);

assign sum = a + b;

endmodule

• Multiplier module:

module Multiplier #(

parameter WIDTH = 16, // total bits including integer and fraction

parameter FRAC = 10 // fractional bits (Q6.10 -> FRAC=10)

)(

input signed [WIDTH-1:0] a,

input signed [WIDTH-1:0] b,

output signed [WIDTH-1:0] out

);

wire signed [2*WIDTH-1:0] out_full;

//full precision out size

assign out_full = a * b; // 16×16 → 32-bit signed

// Shift down from 20 fraction to 10 fraction

// Use arithmetic shift (>>>)

assign out = out_full >>> FRAC;

endmodule

• Register:

module Register #(

parameter WIDTH = 16, // total bits including integer and fraction

parameter FRAC = 10 // fractional bits (kept for interface consistency)

)(

input wire clk, // Clock signal

input wire rst_n, // Active-low synchronous reset

input wire load, // Load / Accumulate enable signal

input signed [WIDTH-1:0] d_in, // Data Input (WIDTH-bit fixed-point)

output reg signed [WIDTH-1:0] q_out // Accumulated Output

);

always @(posedge clk)

begin

if (!rst_n)

q_out <= {WIDTH{1'b0}}; // Dynamically sized zero reset

else if (load)

q_out <= q_out + d_in; // Accumulate only when load is high

// If load is 0, q_out automatically holds its value

end

endmodule

• MAC module:

module MAC#(

parameter WIDTH = 16,

parameter FRAC =3

)(

input wire clk,

input wire rst_n,

input wire load,

input wire signed [15:0] x_in,

input wire signed [15:0] w_in,

output wire signed [15:0] acc_out

);

wire signed [15:0] mul_out;

wire signed [15:0] add_out;

// 1. Multiplier Instance

Multiplier #(

.WIDTH(WIDTH),

.FRAC(FRAC)

) u_mult (

.a(x_in),

.b(w_in),

.out(mul_out)

);

// 2. Adder Instance (Kekal ada: darab + feedback acc_out)

Adder #(

.WIDTH(WIDTH),

.FRAC(FRAC)

)u_add (

.a(mul_out),

.b(acc_out),

.sum(add_out)

);

// 3. Register Instance (PIPO simpan hasil sum dari adder)

Register #(

.WIDTH(WIDTH),

.FRAC(FRAC)

)u_reg (

.clk(clk),

.rst_n(rst_n),

.load(load),

.d_in(add_out),

.q_out(acc_out)

);

endmodule

• test bench module:

module tb_MAC;

parameter WIDTH = 16;

parameter FRAC =10;

reg clk;

reg rst_n;

reg load;

reg signed [15:0] x_in;

reg signed [15:0] w_in;

wire signed [15:0] acc_out;

// Instantiate UUT

MAC#(

.WIDTH(WIDTH),

.FRAC(FRAC)

) uut (

.clk(clk),

.rst_n(rst_n),

.load(load),

.x_in(x_in),

.w_in(w_in),

.acc_out(acc_out)

);

// Clock Generation: 100 MHz (10 ns period)

always #5 clk = ~clk;

initial begin

// Initialize Signals

clk = 0;

rst_n = 0;

load = 0;

x_in = 16'sh0000;

w_in = 16'sh0000;

#100;

// Reset Pulse

rst_n = 1;

load=1;

x_in = 16'hFC2A; w_in = 16'hFD55; #10;

x_in = 16'hFC82; w_in = 16'hFBD0; #10;

x_in = 16'hFC30; w_in = 16'hFEDC; #10;

x_in = 16'hFC13; w_in = 16'hFB3B; #10;

x_in = 16'hFC14; w_in = 16'h047C; #10;

x_in = 16'hFC0E; w_in = 16'h08CE; #10;

x_in = 16'hFC1E; w_in = 16'h03B4; #10;

x_in = 16'hFC2D; w_in = 16'h01E8; #10;

// End the input

x_in = 16'h0000; w_in = 16'h0000;

#20;

$finish;

end

endmodule

Expected Value:
0.6396350860595703

1.553606033325195

1.825395584106445

2.995654106140136

1.896456718444824

-0.2746210098266604

-1.173279762268067

-1.628899574279786

Value in waveform:
0.638671875

2.1904296875

4.65234375

10.474609375

19.849609375

-26.47265625

10.1552734375

19.8544921875

-24.291015625

Hello,

I’m working with a Zynq UltraScale+ and trying to transfer data from the PL to the PS through an HP port, with the data stored in DDR for the CPU running PetaLinux to process:

FPGA → DDR ← CPU (PetaLinux)

I have a custom AXI4 master that writes data to HP0. this port has some limitations, including a maximum burst length of 16 beats and a 128-bit beat size.

The FPGA can generate data at different rates, but I start losing data when I reach around 2 Gbps. With the same design in bare-metal, I can reach approximately 6-7 Gbps without data loss. PetaLinux itself is running from DDR.

Has anyone implemented a similar design or encountered this issue? I’d appreciate any advice on what might be limiting the transfer rate under PetaLinux.

Has anyone gotten an oa or heard back from Nvidia hardware intern roles? I applied and recently my application changed from “application submitted” to “in review “

I’m using a bladeRF 2.0 micro A9 and recently I’ve been facing random FPGA loading issues.Sometimes the FPGA loads perfectly fine, but other times I get these errors:
dev->backend->load_fpga failed: File or device I/O failure
Failed to switch to NULL interface
The strange thing is that I’ve successfully loaded FPGA images multiple times using the same laptop and USB cable before. I’m using Windows 11. Could this be due to insufficient USB power from my laptop, or is there something else I should check?
I’m also considering programming through JTAG to see if that helps. Has anyone faced a similar issue?

I'm trying to add eye scan to a design that includes the Aurora 64B/66B IP Core on a Kintex 7. I've been trying to expose the eyescanreset and eyescantrigger ports from the transceiver, but any combination of settings of the core still ties those to '0' in the gtxe2_channel instantiation file. However, the eyescandataerror port is properly exposed outside of the IP Core.

Since this file is part of the IP Core, I'd have to unmanage it to be able to modify it, correct?

Out of curiosity, I did the same for a Kintex UltraScale, and the ports are correctly passed from the top of the example design all the way to the transceiver.

I guess this is yet another bug in the IP Core library? Or is there something I'm missing when it comes to the eye scan features in the Kintex 7 GTXs?

Vivado 2024.1 and 2025.2, by the way.

https://github.com/FlowsDSL/flowsdsl

Flows is a language and toolchain that compiles C-like code to SystemVerilog. step marks a clock cycle explicitly: the compiler doesn't schedule timing, you do. Within a step, the code becomes combinational logic. Programs are transforms that run concurrently and communicate through queues and wires.

Every generated design records a trace of the program's state on each cycle and streams it to the host, mapped back to source lines, transforms and variables. No simulation needed to see what happened. It's in the hardware from the start.

The example ping responder runs on an Alveo U50, answers pings at 10 Gigabit Ethernet line rate, and starts each reply before the request has finished arriving. It meets timing at 322 MHz. All traces in the documentation were captured on the card. The PCIe and Ethernet platform underneath is custom, with no XDMA or vendor MAC.

The docs are written as a path for software developers: a working ping responder first, timing and clock domains when the trace shows why they matter.

Currently targets the U50 with Vivado 2023.2; details in the README's status section. Questions and critique welcome in Discussions.

If anyone has one collecting dust in their lab or office and is willing to part with it, please let me know your asking price and its current condition.

Please send me a PM with photos of the board if you have one available.
Thanks in advance!

Hello,

I am designing a programmable cartridge for MVS. I have selected the memories and microcontrollers, and I would like to include an FPGA per board in order to do the decoding, therefore, I am not in need of a very dense FPGA with lots of LUTs, but cheap, affordable and easy to work components. Programmation would be done through the microcontrollers, which would also be in charge of programming the memories.

Please, could you recommend a family or line with such characteristics?

Thank you very much in advance!

I'm working on a medical device safety controller on an Artix-7. Nothing too complicated, but the development process is mostly new to me.

One of the real joys I've found is seeing the vast number of warnings that Vivado dumps out. Almost all of them seem meaningless, but as this is a medical device, I want to do my due diligence to make sure I review them as best I can. I'd also like to leave a note, initials, and date on each one as I check them off. This last bit doesn't seem to be well supported.

I've been using Claude to help me through this, and it came up with a python script that I can run after synthesis and implementation. It parses runme.log and generates a csv file where I can add all this information. If I rerun systhesis and implementation and then this script, it will check for changes and mark warnings as new, reviewed, or not seen. It also created a separate tcl script to suppress some of the spamier messages that come from Vivado IP blocks. There are some other bells and whistles too.

My question is this: Is this a good process or an AI fever dream? How do other people approach this problem?

I'm building a neuron accumulator using Fixed-point Q6.10 via Vivado for my final year project (This project was given to me even though i don't like digital electronics that much but I still need to do it). The pic i've clipped is the block diagram for it. That's for non bias and activation function, bias and activation function will be added after i've completed this one first. The thing is my neuron accumulator accumulated twice each address, maybe because of the RAM running 2 clocks per address but I still need to put it.

I've made the modules for adder, multiplier, register and memory. I need help for how to fix this top level module so that it won't accumulate twice in one load after it changes address and how to do it.

here is my email: hafizairi10@gmail.com if anyone will be giving me a hand. please help me, i'm begging😭🙏🏼.

Hello guys, I just started my electronic engineering course at uni and was looking into different things I can do. I kind of got interested in career in semiconductors or robotics fields. I was wondering if it is realistic to start practicing with FPGA boards as first year, since a lot of people that I see in this community started FPGA boards as 3rd year cs students or engineering postgraduates. Also, could you give me some project ideas I could use for the uni fund application. Appreciate all the input, including personal stories, resources, advice etc. :)

Prompted by this recent thread that described a test bench failure caused by a simulated clock not being exactly the right frequency, I thought I'd post a solution for generating test clocks with zero frequency error.

This is not a replacement for the usual clk <= not clk after 5 ns; or clk <= #5 !clk; as these are fine for most use cases and likely more efficient than the method described here.
Instead, this clock generator is meant for things like making two clocks that have an accurate 200 ppm frequency difference for testing clock domain crossers in Ethernet interfaces in simulation, etc.

This is based on a component that I've been using in testbenches for well over 20 years. It's been tested in many different simulators.

I'm presenting a very cut down version to explain the technique. The full version that I use in testbenches (that I'm not posting!) has extra features such as: an enable input, true and inverted outputs (for driving differential inputs), divided outputs, all outputs update in the same delta cycle, settable initial values, a control voltage input (with settable Kv and modulation bw) to simulate VCXOs, etc.

The VHDL version measures the simulator timing resolution. All edges of the output clock are aligned with integer multiples of that time. The Verilog version uses a fixed timing resolution (which may or may not suit any particular frequency).

There will be some jitter on the generated clock as a consequence of the way the output edges are aligned (unless the (half) period is an exact multiple of the timing resolution, of course).

I’m looking to take on freelance work in FPGA, Verilog, embedded, and SoC design. For those of you who freelance or have done so in the past, how do you find opportunities, and how do you approach the right person (the decision-maker) at a company to start a conversation?

Any advice on platforms, networking, or how you got your first clients would be appreciated. Thanks!

Vivado reported timing met on my design, but it still had two unsynchronized clock crossings. So I built FPGA Project Analyzer skill for it:

https://github.com/al-nafisah/fpga-project-analyzer

Point it at a Vivado, Zynq or PYNQ project folder and it gives you a clickable diagram of the design, from block design down to RTL, with wires coloured by clock domain. It also flags unsynchronized clock crossings, missing pin constraints, and common reset, address-map and PYNQ mistakes.

Hi all,

I would love to hear your experience of using AI in RTL coding and building complete projects, what was your experience in writing RTL codes, building full projects from scratch, debugging and achieving timing closure.
Have you tried AMD ross? What do you think about it?

Je me suis amusé avec Claude ce week-end. Ça tourne bien sur FPGA même si pour l'instant c'est plus agréable de lancer une partie de SOR2. Je vais faire des itérations jusqu'à avoir un jeu vraiment sympa.

DigSim: a digital logic simulator in Python that you can also feed Verilog

Hi! DigSim is a logic simulator you can play around with. You drag switches, push buttons, gates, flip-flops, LEDs and 7-segment displays onto a canvas, wire them up, and watch the circuit run live.

Processing img 5azlufgu0nxh1...

Some things it can do:

- Verilog as components. Write a module in the built-in editor, press Ctrl+B, and it becomes a part you can wire up. Yosys does the synthesis and comes bundled, so there's nothing else to install. Modules with parameters work too, so one counter file can give you a 4-bit and a 16-bit copy.

- See what's going on. There's a logic analyzer component, a buzzer, and VCD output you can open in GTKWave.

- Script it from Python. Build circuits in code and write pytest testbenches for your Verilog. One of the examples runs a 6502 CPU.

- It runs on Linux, Windows and macOS.

If you want to try it: pip install digsim-logic-simulator, then python -m digsim.app.
If you use uv, uvx digsim-logic-simulator works too.

- GitHub: https://github.com/freand76/digsim

- Docs, with a getting-started tutorial: https://freand76.github.io/digsim/

It's a hobby project, so it has rough edges. I'd love to hear what you think, what breaks, or what you'd like it to do!