We are building a small research wristwatch with an nRF52840 module and an nPM1300 PMIC (nPM1300-CAAA-R7, WLCSP-35). We are about to build a few prototypes and would like a second opinion on the PMIC area. The images show only this area.
The board
- 4 layers, 0.8 mm. Layer 1 is the top, layer 2 is solid ground, layer 3 is the 2.0 V rail pour with some signals, and layer 4 is the bottom.
- U1 is on the bottom side. The images are seen from the top of the board, so they are not mirrored.
- BUCK1 is set to 2.0 V and BUCK2 to 3.0 V. Both use 2.2 uH, 2.0 x 1.2 mm inductors (L1 and L2) and 10 uF output caps (C7 and C8).
- PVDD is tied to VSYS and has two 10 uF caps (C2 and C3). VSYS has one more 10 uF cap (C4).
The land pattern
- 0.25 mm round NSMD lands, 0.30 mm mask openings, 0.25 mm paste apertures and a 0.10 mm stencil.
- Seven inner balls (B5, B6, C3, C6, D3, D4 and D6) have a 0.15 mm via in pad. The fab fills them with epoxy and caps them flat.
- Tracks neck down to 0.10 mm inside the mask openings.
- Nordic's reference layout uses 0.211 mm lands with 0.363 mm mask openings. We used 0.25 mm lands because that is the smallest land our fab can cap a via in.
Questions
Do you see any problem with this land pattern or the via in pad escape for reliable assembly?
Do the BUCK1 and BUCK2 loops look OK? That means the PVDD caps, the inductors, the output caps and their PVSS returns.
Would you add a small 10 to 100 nF cap on PVDD close to the ball, because the board also has Bluetooth?
Layer 3, right above U1, is a power pour and not ground. Is that a problem for the bucks?
Thanks for any help!